This invention relates to the layout of integrated circuits, and more particularly, to optimal stacked transistor placement in the layout of integrated circuits such that the integrated circuits demonstrate increased robustness when struck by a single event charge.
Integrated circuits are subject to a phenomenon known as single event upset (SEU). A single event upset is a change of state caused by ions or electro-magnetic radiation. Cosmic rays or radioactive impurities embedded in integrated circuits and their packages may be responsible for generating such ions or electro-magnetic radiation.
When ions or electro-magnetic radiation strike the silicon substrate on which the integrated circuit is implemented, electron-hole pairs are generated. The electron-hole pairs create a conduction path that can cause a charged node for example at the input of an inverter circuit to discharge. Thus, a single event upset may cause a logic “1” at the input of the inverter circuit to change to a logic “0”. The change in state from a logic “1” to a logic “0” at the input of the inverter circuit causes the output of the inverter circuit to change from a logic “0” to a logic “1”. The propagation of such a single event through a circuit is sometimes referred to as a single event transient.
Upset events in sequential elements (e.g., memory elements, latches, or registers) or upset events that reach sequential elements as transients when those sequential elements store data can have serious repercussions for system performance. In certain system applications such as remote installations of telecommunications equipment, it is extremely burdensome to repair faulty equipment. Unless an integrated circuit demonstrates good immunity to single event upsets and single event transients, they will be unsuitable for these types of applications.
It would therefore be desirable to be able to improve the single event transient robustness of an integrated circuit.